In the processing of integrated circuits electrical contact must be made to active device regions formed within the wafer substrate typically comprising monocrystalline silicon. The active device regions are connected by highly conductive paths or lines which are fabricated above an insulator material, and which covers the substrate surface. To provide electrical connection between the conductive path and active device regions, an opening or contact is provided. Ultimately, an electrically conductive contact filling material is provided in the contact opening to make electrical contact to the underlying active device region.
It is desirable, during the processing of integrated circuits, to provide an intervening layer to prevent the intermixing of the contact filling materials with silicide and the underlying silicon. Accordingly, this intervening layer is typically provided to prevent the diffusion of the silicon and silicide with an associated plug filling metal and to effectively adhere a plug filling metal to the underlying substrate. Such material is accordingly also electrically conductive and commonly referred to as a "barrier layer" due to the anti-diffusion properties of same. U.S. Pat. No. 5,231,306, and pending application Ser. No. 08/631,235, filed on Apr. 11, 1996, and 08/643,420, filed on May 8, 1996, all assigned to the assignee of the present invention, are directed to the use and fabrication of such barrier layers. The teachings of the aforementioned patent, and pending applications are incorporated by reference herein.
In the formation of a stacked capacitor structure which is employed in a DRAM, a lower electrode is typically electrically connected to another substrate device by means of a polysilicon plug. Normally, a barrier layer separates the polysilicon plug from the lower electrode of the capacitor to prevent both silicon diffusion into the electrode and oxidation of the plug which may be occasioned by the continued processing of the integrated circuit. A DRAM storage node capacitor is formed when a dielectric, or ferroelectric layer is interposed between a lower electrode and an upper electrode. The capacitor is typically covered and protected by a planarized layer of silicon dioxide. The capacitor is accessed by connecting a bit line to the capacitor lower electrode through a word line transistor.
The above design is not without drawbacks. For example, to obtain useful electrical performance, the dielectric or ferroelectric layer is typically deposited or otherwise annealed at high temperature and in an oxygen ambient. Under these processing conditions, oxidation of the underlying barrier layer, polysilicon plug or active area may undesirably occur. If oxide forms, a parasitic capacitor will be created. This parasitic capacitor would be disposed in series with the storage node capacitor. The resulting parasitic capacitor will prevent the full application of voltage to the storage node. This, in turn, will result in a decrease in the amount of charge which can be stored by the capacitor.
To address this problem, semiconductor processors have typically utilized a layer of a noble metal or conductive oxide as the lower electrode of the storage node capacitor so that the electrode is conductive following dielectric deposition. In this physical arrangement, the electrode and barrier layer, in combination, protect the polysilicon plug from oxidation. Further, the underlying transistor is protected from oxygen by silicon dioxide and the polysilicon plug. Still further, the barrier layer also prevents silicon diffusion from the polysilicon plug to the lower electrode. It has been discovered that if silicon diffuses through the lower electrode to the dielectric layer, this diffusing silicon can subsequently oxidize thereby forming a parasitic silicon dioxide capacitor, or in the alternative, the silicon reacts with the dielectric and decreases the dielectric constant of the layer. This condition may also increase the leakage current.
It would be desirable, therefore, to improve upon the design of a capacitor electrode in a method for forming a capacitor electrode which achieves the benefits to be derived from prior fabrication techniques, but avoids the detriments individually associated therewith.